After a semiconductor or silicon wafer is produced it is processed through a variety of tests to ensure that it works as intended. One of the test tooling units places contacts onto the connection bumps of each die to test bump integrity and also to test for shorts and grounds. Currents are applied to each connection bump of each die. Among the tests are measurements of currents that occur from applied voltages and currents. If there is a failure at one or more of the connection bumps of a die during a test, however, there may be an over current condition at the connection bump. This may propagate through the test tool and damage the test tool. Wafer test tooling, for example, a Sort Interface Unit (SIU) has no ability to protect itself from individual wafer bump or probe level failures while testing silicon wafers. As a result, the service life of the test tooling is reduced.
Damage to the tool can be mitigated by modifying the test program that controls the automated test equipment (ATE testers). However, this approach does not correct for the failure of individual probes and is too slow to protect against overcurrent power supply clamping events. Damage can also be mitigated by increasing the current carrying capabilities of the wafer probes. However, the current carrying ability of a probe is determined by the physical dimensions of the probe so that as the connection bumps become closer together with future chip generations, the size of the probes must also be reduced. Larger, higher current probes cannot be used when the connection points are very close together. The effects of over current can also be mitigated using modification of the printed circuit boards of the test tooling. However such circuitry cannot address failures at a particular probe because the connections to multiple probes are combined together at the printed circuit board. In addition, due to the long leads from each probe to the printed circuit board the response time is too slow for overcurrent events.